Evaluation of a ´stall´ cache: an efficient restricted onchip instruction cache

The paper compares the cost and performance of a new kind of restricted instruction cache architecture-the stall cache-against several other conventional cache architectures. The stall cache minimizes the size of an onchip instruction cache by caching only those instructions whose instruction fetch phase collides with the memory access phase of a preceding load or store instruction. Many existing machines provide a single cycle external cache memory. The results show that, under this assumption, the stall cache always outperforms an equivalent sized on-chip instruction cache, reducing external memory access stalls by approximately 10%. In addition results are presented for a system using an on-chip data cache, and for one with a double width data bus and short instruction prefetch buffer.