A simulation study of snoopy cache coherence protocols

Snoopy protocols represent a very popular class of hardware cache coherence solutions, especially suitable for bus-based, shared memory multiprocessors. It is not firmly established which of the two main approaches (write-invalidate or write-broadcast) is superior over the wide range of applications. An enhancement of write-invalidate protocols is proposed, introducing the word invalidation capability. Simulations with a synthetic workload model were performed, in order to analyze its behavior, and to compare it with the best representatives of write-invalidate and write-broadcast protocols. Performance evaluation was done for simulated workloads with a lower and a higher degree of sharing, as well. An attempt is made to model some effects of process switching and migration. Finally, some implications of using a more advanced bus technology on snoopy protocols performance is discussed.