Comparison and evaluation of two catalytic migration approaches for the design of windowing-oriented register file structures

The authors give an overview of catalytic migration methodology for processor design in conditions typical of GaAs technology (small chips and large ratio of off-chip to on-chip delays), concentrating on the application of catalytic migration approaches to register file design. Two original approaches for the design of small register files are presented, analyzed, and compared with previous approaches. The advantages and disadvantages of these new approaches to register file design are discussed, and the conditions under which they work better than previous approaches are outlined. Design tradeoffs are examined in an analytic study.