Transformation-based high-level synthesis of fault-tolerant ASICs

The authors present a transformation-based approach to the high-level synthesis of fault-tolerant application-specific ICs (ASICs) satisfying a given performance constraint but requiring less than proportional increase in hardware over their nonredundant counterparts. They propose a synthesis methodology to exploit hardware minimizing transformations. A simple set of transformations are identified that minimize the fault-tolerance overhead. The selected transformations make the final design resilient to common mode failures. These transformations can be composed to form a rich set of complex transformations. An algorithm is presented to automatically identify structures in a flow graph where transformations can improve hardware utilization, and transformations that suit the structure best are applied. The system has been used to schedule several flow graphs.