Title :
Logic decomposition for programmable gate arrays
Author :
T. Luba;M. Markowski;B. Zbierzchowski
Author_Institution :
Inst. of Telecommun., Warsaw Univ. of Technol., Poland
fDate :
6/14/1905 12:00:00 AM
Abstract :
In this paper an effective decomposition algorithm for mapping of logic functions onto FPGAs is proposed. The algorithm exploits the symbolic decomposition concept to find FPGA based implementation with a minimal number of CLBs. Experimental results of the presented method are provided and compared to other similar tools.
Keywords :
"Programmable logic arrays","Boolean functions","Field programmable gate arrays","Input variables","Logic functions","Logic arrays","Gold","Calculus","Cost function"
Conference_Titel :
Euro ASIC ´92, Proceedings.
Print_ISBN :
0-8186-2845-6
DOI :
10.1109/EUASIC.1992.228064
