DocumentCode :
3622974
Title :
I-path analysis
Author :
J. Blatny;Z. Kotasek;J. Hlavicka
Author_Institution :
Dept. of Comput. Sci. & Eng., Tech. Univ. of Brno, Czech Republic
fYear :
1993
fDate :
6/15/1905 12:00:00 AM
Firstpage :
255
Lastpage :
262
Abstract :
A circuit at the register transfer level is denoted as an RTL circuit. The paper describes a method for extracting the RTL circuit structure from the circuit formal description, using the I-path concept. The way of representing the RTL circuit structure by a labelled directed graph where nodes represent components and arcs represent connections between them, is presented. Labels identifying the component type are attached to the nodes, and other labels are attached to arcs to identify attributes of connections. It is shown, how the graph theory algorithms can be used to derive the information about the accessibility of circuit components, i.e., the existence of I-paths between them, and the sequences of control and clock signals which must be generated to transfer the information along the existing I-paths.
Keywords :
"Circuit testing","Registers","System testing","Time division multiplexing","Test pattern generators","Logic testing","Databases","Graph theory","Design for testability","Kernel"
Publisher :
ieee
Conference_Titel :
European Test Conference, 1993. Proceedings of ETC 93., Third
Print_ISBN :
0-8186-3360-3
Type :
conf
DOI :
10.1109/ETC.1993.246561
Filename :
246561
Link To Document :
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