Title :
A VLSI-chip for a hardware-accelerator for the simplex-method
Author :
B. Schutz;A. Klindworth
Author_Institution :
Dept. of Comput. Sci., Hamburg Univ., Germany
fDate :
6/14/1905 12:00:00 AM
Abstract :
A hardware realization of the simplex method, the central method of linear programming, a presented. the algorithm is customized for numerical stability (arithmetics) as well as hardware proximity. The resulting hardware is based on a parallel architecture with up to eight processing units, employing standard floating point units (FPUs), RAMs, and custom VLSI chips. It has been designed for use in an IBM PC/AT environment.
Keywords :
"Hardware","Linear programming","Computer architecture","Numerical stability","Mathematical model","Computer science","Read-write memory","Floating-point arithmetic","Roundoff errors","Data structures"
Conference_Titel :
ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Print_ISBN :
0-7803-0768-2
DOI :
10.1109/ASIC.1992.270201
