A survey of hardware solutions for maintenance of cache coherence in shared memory multiprocessors

Appropriate solution of the well-known cache coherence problem in shared memory multiprocessors is one of the key issues in improving the performance and scalability of these systems. Hardware methods are convenient because of their transparency for software. They also offer good performance since they deal with the problem dynamically. Hardware cache coherence schemes can be principally divided into two large groups: directory and snoopy protocols. This survey underlines their principles and summarizes a relatively large number of relevant representatives from both groups. The coherence problem in multilevel caches is also briefly considered. Special attention is devoted to cache coherence maintenance in large scalable shared memory multiprocessors.