Architectural requirements for multimedia image compression, and a solution based on VLSI hardware accelerator

A VLSI hardware accelerator is proposed for improving the performance of a class of image compression techniques, used in multimedia applications. First, we introduce the concept of hardware accelerators relative to the environment under consideration. After that, we give a possible classification of image compression techniques, from the architecture requirements point of view, with a focus on a class of techniques for which the improvement is proposed. Finally, we introduce the proposed hardware accelerator solution, analyze the expected performance improvement, and discuss the implementational complexity. In conclusion, we present our plans for future work on the subject.