A functionality fault model: feasibility and applications

This paper introduces a functionality fault model and demonstrates its feasibility and advantages. In current designs, the fanin of logic modules implemented in CMOS standard cell, mask-programmable, or field-programmable gate array technology, rarely exceeds 4 on the average. A functionality fault model, based on complete enumeration of the truth table of each logic module, is thus entirely feasible and enhances the quality of the test significantly. Tests based on this model provide complete coverage of module´s behavior, interior faults as well as input stuck-at and bridging faults of any multiplicity/spl minus/reducing the need for technology and implementation-specific fault models, The paper also introducer, techniques that lead to efficient implementation of a prototype test generation system and demonstrates its application not only to generate high quality test patterns but also to generate functionality don´t cares that can optimize logic and wiring even after mapping a design into a given technology.