DocumentCode :
3623326
Title :
Self-timed adder with pipelined output
Author :
H. Dhanesha;A. Albicki
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
fYear :
1993
Firstpage :
855
Abstract :
This paper presents the design of a self-timed adder, with event driven logic and pipelined output. The scheme makes the individual outputs of bit-wise additions independent of the preceding bits, resulting in high throughput at the cost of initial latency and hardware overheads. Simulation results based on parameters extracted from VLSI implementation of a model 4-bit adder are used to illustrate the performance. The design was implemented with transmission gates in 2-micron CMOS technology. Expansibility to larger adders is shown to give the same performance benefits.
Keywords :
"Delay","Hardware","Logic design","Throughput","Clocks","Rails","Pipelines","CMOS technology","Multivalued logic","Signal generators"
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Print_ISBN :
0-7803-1760-2
Type :
conf
DOI :
10.1109/MWSCAS.1993.343203
Filename :
343203
Link To Document :
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