A gate array chip for high frequency DSP applications

A gate array architecture for high speed correlation and convolution is described. A gate array chip based on this architecture is designed and an FIR filter is implemented on this chip. Bit-level array in pipeline structure is used in the architecture. For high I/O data rate, true single phase clocking circuit technique in CMOS is applied. The gate array chip is designed in 1.2 /spl mu/m CMOS with the programming layer metal-2 only. Spice and Verilog simulations show that the throughput is over 100 MHz.