Systolic VLSI implementations of a Galois field arithmetic algorithms

Two systolic architectures that implement the algorithms for multiplication, division and exponentiation operations in GF(2/sup m/) are presented. The architectures are systolic and capable of producing a new result every clock cycle. Two prototype VLSI chips, SIGMA (for multiplication/division) and ACE (for exponentiation), have been designed using 2 micron CMOS technology. Both SIGMA and ACE are implemented for the GF(2/sup 4/) and are programmable to select between different irreducible polynomials. The chips can yield a computational rate of 40 million operations per second.