A new approach to reconfigure faulty systolic arrays

Reconfiguration problems for tightly coupled array processors, such as systolic arrays, with sparse and clustered faults are addressed. A new approach based on structural reconfiguration is developed in conjunction with a two-layer array topology. Two data flow strategies are also developed to optimize cell utilization. By varying the design parameters, a range of reconfiguration algorithms can be devised with different survivability and cost ratios.