DocumentCode :
3623776
Title :
Full-Chip Inductance Modeling and Simulation: Breaking the Complexity not Accuracy Bottleneck
Author :
Eli Chiprout
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Firstpage :
111
Lastpage :
111
Keywords :
"Inductance","USA Councils","Timing","Chip scale packaging","Filters","Databases","Robustness"
Publisher :
ieee
Conference_Titel :
Signal Propagation on Interconnects, 6th IEEE Workshop on. Proceedings
Print_ISBN :
0-7803-9821-1
Type :
conf
DOI :
10.1109/SPI.2002.258296
Filename :
4027671
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3623776