DocumentCode :
3623819
Title :
Analysis of One Step Majority Logic Decoders Constructed From Faulty Gates
Author :
Shashi Kiran Chilappagari;Milos Ivkovic;Bane Vasc
Author_Institution :
Dept. of Electrical and Computer Eng., University of Arizona, Tucson, AZ 85721, USA. Email: shashic@ece.arizona.edu
fYear :
2006
fDate :
7/1/2006 12:00:00 AM
Firstpage :
469
Lastpage :
473
Abstract :
In this paper we propose an analytical method to evaluate the performance of one step majority logic decoders constructed from faulty gates. We analyze the decoder under the assumption that the gates fail independently. We calculate the average bit error probability of such a decoder and apply the method to the special case of projective geometry codes. The method, however, applies to any regular low-density parity-check code of girth at least six but the calculations are much simpler for the projective geometry codes. We present results for the bit error rate performance of four codes from projective planes
Keywords :
"Decoding","Circuit faults","Error correction","Redundancy","Parity check codes","Logic gates","Logic circuits","Mathematics","Performance analysis","Information geometry"
Publisher :
ieee
Conference_Titel :
Information Theory, 2006 IEEE International Symposium on
ISSN :
2157-8095
Print_ISBN :
1-4244-0505-X
Electronic_ISBN :
2157-8117
Type :
conf
DOI :
10.1109/ISIT.2006.261713
Filename :
4036005
Link To Document :
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