DocumentCode
3623945
Title
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines
Author
Laura Pozzi;Paolo Ienne;Christophe Dubach;Miljan VuletiC
Author_Institution
Ecole Polytechnique F?d?rale de Lausanne (EPFL), Lausanne, Switzerland
fYear
2005
Firstpage
243
Lastpage
248
Abstract
The performance of virtual machines (e.g., Java Virtual Machines---JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from software to reconfigurable hardware. In contrast to the compile-once-run-anywhere concept of virtual machines, reconfigurable applications lack portability and transparent SW/HW interfacing: applicability of accelerated hardware solutions is often limited to a single platform. In this work, we apply a virtualisation layer that provides portable and seamless integration of hardware and software components to a Java Virtual Machine platform, making it capable of accelerating any Java bytecode method by using platform-independent hardware accelerators. The virtualisation layer not only improves portability of accelerated Java bytecode applications, but also supports runtime optimisations and enables unrestricted automated synthesis of arbitrary Java bytecode to hardware. To show the advantages and measure the limited overheads of our approach, we run several accelerated applications (handwritten and synthesised) on a real embedded platform. We also show our synthesis flow and discuss its advanced features fostered by the virtualisation layer.
Keywords
"Hardware","Virtual machining","Application software","Java","Acceleration","Field programmable gate arrays","Software performance","Permission","Microprocessors","Programmable logic arrays"
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis, 2005. CODES+ISSS ´05. Third IEEE/ACM/IFIP International Conference on
Print_ISBN
1-59593-161-9
Type
conf
DOI
10.1145/1084834.1084896
Filename
4076344
Link To Document