• DocumentCode
    3624093
  • Title

    Using Reconfigurable HW for High Dimensional CAF Computation

  • Author

    Antonin Hermanek;Michal Kunes;Michal Kvasnicka

  • Author_Institution
    Institute of Information Theory and Automation, Academy of Sciences of the Czech Republic, Prague, Czech Republic, email: hermaneke@utia.cas.cz
  • fYear
    2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In modern radio location systems based on passive coherent location (PCL), one of the key problems is an efficient and accurate computation of the cross ambiguity function (CAF). This function is related to the direct signal and signals reflected from localized targets. CAF represent power spectral density distribution of the cross-correlation between direct and reflected signals. In this paper we present an attempt to implement (numerically effective and sufficiently accurate) the CAF computation accelerator on FPGA. The results show that this accelerator could be used to compute CAF in real-time in the future PCL systems. The presented design has been implemented in PC accelerator cards based both on Xilinx Virtex IV and Altera Stratix II devices. The presented contribution gives overall information about the algorithms, accelerator architecture design and achieved performance. The possibilities of the future enhancements are discussed.
  • Keywords
    "Frequency","Field programmable gate arrays","Signal processing algorithms","Delay effects","Real time systems","Signal processing","Engines","Radio transmitters","Signal resolution","Floating-point arithmetic"
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2006. FPL ´06. International Conference on
  • ISSN
    1946-147X
  • Print_ISBN
    1-4244-0312-X
  • Electronic_ISBN
    1946-1488
  • Type

    conf

  • DOI
    10.1109/FPL.2006.311280
  • Filename
    4101042