ASIC DFT techniques and benefits

This tutorial provides an overview of market prospective on and use of the ASIC DFT, DFT techniques (their benefits and drawbacks), and the ASIC DFT process flow. What is needed to do a testable ASIC is discussed. Testability must be incorporated in all phases of the design from embedded blocks, chip level, to board and system level in order to meet the aggressive design-to-volume times. There is cost overhead for DFT but the cost of not using DFT in complex designs is far more. Re-use of DFT techniques at different levels (module, board, and system) spreads the DFT cost over multiple levels of packaging. Use of scan and JTAG DFT techniques simplifies manufacturing tester requirements. A fully testable device/system increases productivity of design and manufacturing groups; lowers manufacturing test and debug costs; lowers costs of system and board rework; enhances product time to volume; and increases product confidence in the end user.