Title :
2.5 Gbit/s PRBS Generator and Checker
Author :
Leon Pavlovic;Matjaz Vidmar;Saso Tomazic
Author_Institution :
Radiation and optics laboratory, Faculty of Electrical Engineering, University of Ljubljana, Tr?a?ka 25, 1000 Ljubljana, Slovenia. E-mail: leon.pavlovic@fe.uni-lj.si
fDate :
6/1/2006 12:00:00 AM
Abstract :
A novel approach in the implementation of a high-speed linear-feedback shift register (LFSR) using a single D-flip-flop is presented. A PRBS data generator and checker using discrete-logical devices are presented as an example. Due to the discrete-logical components used, special device-interconnection techniques must be used to reduce the signal-integrity problems and optimize the device interconnection for optimal system performance
Keywords :
"Delay lines","Propagation delay","Impedance","Transmission lines","Clocks","Packaging","Capacitance","Integrated circuit interconnections","Frequency","Laboratories"
Conference_Titel :
Multimedia Signal Processing and Communications, 48th International Symposium ELMAR-2006 focused on
Print_ISBN :
953-7044-03-3
DOI :
10.1109/ELMAR.2006.329585
