• DocumentCode
    3625199
  • Title

    Flexible Ultra Low Power Successive Approximation Analog-to-Digital Converter with Asynchronous Clock Generator

  • Author

    Rafal Dlugosz;Vincent Gaudet;Kris Iniewski

  • Author_Institution
    Univ. of Neuchatel, Neuchatel
  • fYear
    2007
  • fDate
    4/1/2007 12:00:00 AM
  • Firstpage
    1649
  • Lastpage
    1652
  • Abstract
    An ultra low power 8-bit current-mode successive approximation (SAR) analog-to-digital (ADC) converter for wireless sensor network (WSN) applications is presented. The proposed ADC contains a new asynchronous clock generator, which works only during data processing and is turned off afterwards, thus enabling a power saving mode. The clock generator is controlled by a bias current, and can be adjusted for a wide range of sampling frequencies. The proposed ADC with the clock generator occupy a chip area of 3500 mum2 and dissipate 400 nW power from a 0.6 V supply voltage in a CMOS 0.18-mum technology, enabling input data processing with a frequency of 100 kHz.
  • Keywords
    "Analog-digital conversion","Clocks","Power generation","Wireless sensor networks","Data processing","Frequency","CMOS technology","Sampling methods","Voltage","CMOS process"
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 2007. CCECE 2007. Canadian Conference on
  • ISSN
    0840-7789
  • Print_ISBN
    1-4244-1020-7
  • Type

    conf

  • DOI
    10.1109/CCECE.2007.412
  • Filename
    4233071