Power Analysis Resistant SRAM

The power consumption of a standard CMOS SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure presented in this work reduces the dependency of power consumption on data and address 10 times compared to standard SRAM at the expense of higher power and silicon area consumption. Modifications on the primitive SRAM cell, address decoding logic and write operation were made to reduce the dependency.