Ultra-flexible, layout-enabled field plates for HV transistor integration in SOI-based CMOS

Field plates are commonly used to enhance the performance of high voltage devices and to improve the trade-off between breakdown voltage and specific on-resistance, but they typically require dedicated extra process steps. This paper presents a novel concept of field plate implementation in baseline SOI-CMOS by means of a smart layout without extra processing steps. Such layout-enabled field plates are experimentally demonstrated in a 130 nm SOI-CMOS process, showing a breakdown voltage up to 60 V (3-4x improvement compared to a traditional extended-drain MOSFET). These layout-enabled field plates allow an ultimate flexibility in device optimization, e.g. for multiple voltage domains, robust safe-operating-area and high-frequency power switching.