Test Pattern Compression Based on Pattern Overlapping

This paper describes a test data compression method based on pattern overlapping. We report here improvements that have been done on the test pattern compaction and compression algorithm called COMPAS. This algorithm reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. It compresses the test patterns by overlapping patterns originally generated by an ATPG. The problem of the COMPAS algorithm is that it has to manipulate with enormous amount of data when compressing test sets of large circuits and the CPU time grows rapidly with the growing number of test vectors. These disadvantages were solved by using a test vector initial encoding by sparse vectors and by using a dynamic structure for storing the pre-calculated parameters of candidate vectors to be used in the near future algorithm loops for overlapping with the actual scan chain content. This arrangement allows the algorithm to skip unnecessary computations. The improvements cause that the CPU time grows approximately linearly with the size of the tested circuit. The improved algorithm is also capable to compress data generated by concurrently working ATPG processes.