Clockless Implementation of LEON2 for Low-Power Applications

Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design flow that is used for the de-synchronization works with a synthesizable HDL specification of the circuit, using the conventional synchronous HDL constructs. Standard synchronous design tools can be used, however, in a more elaborate way. The de-synchronized LEON2 processor could provide a low power, low EMI, clock-jitter-free and clock-skew-free solution of a full featured opensource 32-bit processor.