• DocumentCode
    3625775
  • Title

    Power Dissipation in Basic Global Clock Distribution Networks

  • Author

    Artur L. Sobczyk;Arkadiusz W. Luczyk;Witold A. Pleskacz

  • Author_Institution
    Warsaw University of Technology, Institute of Microelectronics and Optoelectronics ul. Koszykowa 65, 00-661 Warsaw, Poland. A.Sobczyk@elka.pw.edu.pl
  • fYear
    2007
  • fDate
    4/1/2007 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In the paper power dissipation and maximal frequency of basic global clock distribution networks is analyzed. Basic topologies of trees and meshes were implemented and simulated in AMS CMOS 0.35 mum technology. Also, a circuit of basic ring oscillator was designed. The comparison of power dissipation and maximal working frequency between those structures was performed.
  • Keywords
    "Power dissipation","Clocks","Frequency","CMOS technology","Circuit simulation","Wires","Parasitic capacitance","Signal generators","Ring oscillators","Energy consumption"
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS ´07. IEEE
  • Print_ISBN
    1-4244-1161-0
  • Type

    conf

  • DOI
    10.1109/DDECS.2007.4295287
  • Filename
    4295287
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3625775