DocumentCode :
3626594
Title :
Equalized interconnects for on-chip networks: modeling and optimization framework
Author :
Byungsub Kim; Vladimir Stojanovic
Author_Institution :
Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139, USA
fYear :
2007
Firstpage :
552
Lastpage :
559
Abstract :
This paper presents a modeling framework for fast design space exploration and optimization of equalized on-chip interconnects. The exploration is enabled by cross-layer modeling that connects the transistor and wire parameters to link performance, equalization coefficients, and architecture-friendly metrics (delay, energy-per-bit, and throughput density). Appropriate models are derived to speed-up the search by more than two orders of magnitude and make a million point design space searchable in less than two hours on a standard machine. With this approach we are able to find the best link design for target throughput, power and area constraints, thus enabling the architectural optimization of energy-efficient on-chip networks. For the same latency and throughput density, equalized interconnects optimized using the new methodology have up to 10times better energy-efficiency than optimized repeater interconnects.
Keywords :
"Network-on-a-chip","Throughput","Design optimization","Delay","Energy efficiency","Optimization methods","Space exploration","Wire","Constraint optimization","Repeaters"
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on
ISSN :
1092-3152
Print_ISBN :
978-1-4244-1381-2
Electronic_ISBN :
1558-2434
Type :
conf
DOI :
10.1109/ICCAD.2007.4397323
Filename :
4397323
Link To Document :
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