DocumentCode
3626628
Title
Tool for Simulation and Optimization BIST Structures
Author
Ireneusz Gosciniak
Author_Institution
University of Silesia / Institute of Computer Science, Sosnowiec, Poland, e-mail: ireneusz.gosciniak@us.edu.pl
fYear
2007
Firstpage
2256
Lastpage
2262
Abstract
Construction of simulation tool for BIST (build in self test) structures verifying and optimization was described in the paper. This tool uses ISCAS´89 benchmarks as testing circuits. Any testing structures for single and multimodular circuits can be described by means of this tool. Form of testing structures notation is similar to attribute format of VHDL language. Because of large generality this tool is used in process of testing structure verification. A short example of testing structure description was presented in the paper.
Keywords
"Built-in self-test","Circuit testing","Circuit simulation","Computational modeling","Automatic testing","Genetic algorithms","Data structures","Feedback","Shift registers","Algorithm design and analysis"
Publisher
ieee
Conference_Titel
EUROCON, 2007. The International Conference on "Computer as a Tool"
Print_ISBN
978-1-4244-0812-2
Type
conf
DOI
10.1109/EURCON.2007.4400365
Filename
4400365
Link To Document