Extremely low-jitter FPGA based synchronization timing system

Injection-involved synchronization timing system must provide synchronization triggers and clocks with the jitter values in the range of few tens of ps. A well-thought-out system-level design approach was necessary, splitting a design into several sub-modules, each addressing the specific synchronization issue. Tight synchronization between the unrelated RF signal and external trigger is based on a PLL phase-shifted over-sampling technique. Beam-monitoring instrumentation synchronization is also handled. An emphasis was put into a design, offering an installation without calibration. Utilizing state-of-the art FPGA circuits we designed a purely digital system, without analogue components (i.e. delay lines) that would require a time-consuming calibration and lead to increasing jitter for long delay ranges. Finally, regardless of its complexity the timing solution has to provide seamless integration into the accelerator facility. To leverage the performance, offered by a dedicated state-of- the-art HW, with flexibility, offered by a SW solution, we used a standard device for peripheral CS integration, based on an embedded processor running OS - a part of a microIOC family of products.