High Throughput Parallel Decoder Design for LDPC Convolutional Codes

LDPC convolutional code (LDPC-CC) decoders are composed of processors, making them parallel in the iteration dimension. However, for time-varying LDPC-CCs, each individual processor is serial in the node dimension, hindering the throughput increase for such decoders. We propose a joint code-decoder design, which generates architecture-aware LDPC- CCs of good performance, as well as an LDPC-CC decoder architecture parallel in the node dimension. Without increase in the memory bits used, the parallel decoder can achieve throughputs at the level of Gb/s with small parallelization factors.