DocumentCode
3629518
Title
Efficient Test Pattern Compression Method Using Hard Fault Preferring
Author
Jiri Jenicek
Author_Institution
Tech. Univ. of Liberec, Liberec
fYear
2008
Firstpage
703
Lastpage
708
Abstract
This paper describes new compression method that is used for test pattern compaction and compression in algorithm called COMPAS, which utilizes a test data compression method based on pattern overlapping. This algorithm reorders and compresses deterministic test patterns previously generated in an ATPG by overlapping them. Independency of COMPAS on used ATPG is discussed and verified. New method improves compression ratio by preprocessing input data to determine the degree of random test resistance for each fault. This information allows the algorithm to reorder test patterns more efficiently and results to 10% compression ratio improvement in average. Compressed data sequence is well suited for decompression by the scan chains in the embedded tester cores.
Keywords
"Circuit testing","Automatic test pattern generation","Circuit faults","Test pattern generators","Integrated circuit testing","Fault detection","System testing","Test data compression","Hardware","Electrical fault detection"
Publisher
ieee
Conference_Titel
Digital System Design Architectures, Methods and Tools, 2008. DSD ´08. 11th EUROMICRO Conference on
Print_ISBN
978-0-7695-3277-6
Type
conf
DOI
10.1109/DSD.2008.88
Filename
4669305
Link To Document