DocumentCode :
3629520
Title :
On Lookup Table Cascade-Based Realizations of Arbiters
Author :
Petr Mikusek;Vaclav Dvorak
Author_Institution :
Brno Univ. of Technol., Brno
fYear :
2008
Firstpage :
795
Lastpage :
802
Abstract :
This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability.
Keywords :
"Table lookup","Iterative algorithms","Boolean functions","Microprogramming","Data structures","Field programmable gate arrays","Circuit synthesis","Sequential circuits","Prototypes","Digital systems"
Publisher :
ieee
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2008. DSD ´08. 11th EUROMICRO Conference on
Print_ISBN :
978-0-7695-3277-6
Type :
conf
DOI :
10.1109/DSD.2008.74
Filename :
4669317
Link To Document :
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