Title :
Background ADC calibration in digital domain
Author :
Cheongyuen Tsang;Yun Chiu;Johan Vanderhaegen;Sebastian Hoyos;Charles Chen;Robert Brodersen;Borivoje Nikolic
Author_Institution :
University of California, Berkeley, 94704, USA
Abstract :
A 100MS/s pipelined ADC is digitally calibrated by a slow ΣΔ ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411kHz sinusoidal input, the peak SNDR improves from 28dB to 59dB and the SFDR improves from 29dB to 68dB. The complete 0.13μ ADC SoC occupies a die size of 3.7mm×4.7mm, and consumes a total power of 448mW.
Keywords :
"Calibration","Voltage","Pipelines","Operational amplifiers","Transfer functions","Error correction","CMOS digital integrated circuits","CMOS analog integrated circuits","CMOS technology","Digital filters"
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
2152-3630
DOI :
10.1109/CICC.2008.4672081
