Title :
Implementation of AES algorithm resistant to differential power analysis
Author :
Marek Strachacki;Stanislaw Szczepanski
Author_Institution :
Graphics Development Group, Intel Technology Poland, ul. Slowackiego 173, 80-298 Gdansk, Poland
Abstract :
This paper describes differential power analysis (DPA) of encryption algorithms hardware implementations. Proposed DPA-resistant design method combines power equalization for synchronous and combinatorial circuits. AES algorithm has been implemented in Xilinx Spartan II-E field programmable gate array (FPGA) device using the standard and DPA-resistant methods. XPower tool has been introduced to collect power traces for DPA. Results show that the standard AES implementation can be broken using DPA in N=2000 encryption operations. At the same time DPA of modified AES implementation for N=2000 encryption operations does not show any correlation between power consumption and the cipher key.
Keywords :
"Algorithm design and analysis","Cryptography","Energy consumption","Hardware","Field programmable gate arrays","Performance analysis","Application specific integrated circuits","Testing","Design methodology","Performance evaluation"
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Print_ISBN :
978-1-4244-2181-7
DOI :
10.1109/ICECS.2008.4674829
