N-meander scanning trace a method for the on-chip bandwidth reduction

In video processing, a multilevel memory hierarchy is a typical answer to the high off-chip bandwidth requirements. Multilevel memory hierarchies reduce the number of the off-chip memory accesses by moving them within the memory hierarchy. This results in the increased on-chip memory bandwidth, which influences the power consumption and performance. This is especially visible in applications that require large memory capacity, such as motion estimation and compensation. In this paper, we present a method to reduce the on-chip memory bandwidth, under the moderate memory capacity increase. Our method allows the trade-off between the on-chip bandwidth reduction factor (for example 4 times) and the memory capacity increase (for example 20%). With both cases, the off-chip memory bandwidth is intact. The method does not impair the algorithmic quality, which we show on the example of a high-quality motion estimation algorithm used in video post-processing. Also, the method enables higher utilization of processing resources.