Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution

An outstanding challenge for realizing nanoelectronic systems is nano-interface design, i.e., how to precisely access a nanoscale wire in an array for communication between a nanoscale system and the outside world. Existing nanoelectronic addressing methods are based on implementation of binary decoders, which requires unrealistic precise layout design in nanotechnology. In this paper, I propose voltage controlled nanoelectronic addressing, which differentiates each nanoscale wire by their electrical parameters, e.g., voltages, instead of required unique physical structures. As a result, voltage controlled nanoelectronic addressing achieves significant yield improvement, which enables aggressive scaling of nano-interface with the rest of a nanoscale system. A novel nanoelectronic addressing circuit includes two address lines which form resistive voltage dividers, and provide gate voltages for two rows of transistors which gate the nanoscale data lines. For two proposed nanoelectronic addressing metrics: resolution and accuracy, the proposed circuit achieves single data line resolution by applying high voltage drops to the address lines if not high subthreshold slope transistors, while an adaptive addressing method achieves addressing accuracy only depending on the uniformity of the address lines, and external time domain variations. SPICE simulation based on compact CNFET models demonstrates the effectiveness of voltage controlled nanoelectronic addressing.