Title :
Latent interface-trap generation during thermal annealing of /spl gamma/-ray irradiated power VDMOSFETs
Author :
A. Jaksic;G. Ristic;M. Pejovic
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Serbia
Abstract :
The behaviour of the threshold voltage in commercial n-channel power VDMOSFETs during biased thermal annealing, following /spl gamma/-ray radiation exposure, is investigated. It is found that ´rebound´ effect, observed in transistors irradiated and annealed with positive gate bias, is mainly due to the ´latent´ interface-trap generation. Possible mechanism for latent interface-trap buildup is proposed.
Keywords :
"Power generation","Annealing","Threshold voltage","Electron traps","Power MOSFET","MOSFET circuits","Communication switching","Temperature measurement","Power engineering and energy","Thermal engineering"
Conference_Titel :
Semiconductor Conference, 1995. CAS´95 Proceedings., 1995 International
Print_ISBN :
0-7803-2647-4
DOI :
10.1109/SMICND.1995.494901
