An approach to processor logic design using HDL for silicon compilation

This paper describes one approach to processor design, based on the utilization of HDLs for silicon compilation, in conditions when the transistor count of the target chip is extremely large. The general design methodology is presented in the first part of the paper. Then, the details of a 64-bit superscalar processor design model in ISP´ hardware description language are shown. We discuss our experience related to testing at the end.