Multiplexing/demultiplexing system of television components at 229.5 Mbps

The authors describe the architecture of a synchronous time division multiplexing/demultiplexing system of the television components standard requiring a 229.5 Mb/s bit rate. They also describe some tradeoffs they had to make in the implementation. The multiplexing structure is word interleaved with the following order: B-Y, Y, R-Y, Y, B-Y, Y, R-Y, Y, B-Y, etc. The work sequence (B-Y, Y, R-Y) corresponds to the samples of luminance and chrominance in the same image dot and the following word Y corresponds to the luminance sample of the neighbor image dot. Descriptions of the emitter and receiver blocks are given.