DocumentCode
3631539
Title
Asynchronous two-level logic of reduced cost
Author
Igor Lemberski;Petr Fiser
Author_Institution
Baltic International Academy, Riga, Latvia
fYear
2009
Firstpage
68
Lastpage
73
Abstract
We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.
Keywords
"Costs","Logic circuits","Minimization","Logic design","Design methodology","Propagation delay","Delay estimation","Computer science","Circuit synthesis","Signal synthesis"
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS ´09. 12th International Symposium on
Print_ISBN
978-1-4244-3341-4
Type
conf
DOI
10.1109/DDECS.2009.5012101
Filename
5012101
Link To Document