A symbolic RTL synthesis for LUT-based FPGAs

In this paper a methodology of symbolic RTL synthesis, for circuits implemented in FPGA devices, is presented. First, symbolic functions are separated from binary and arithmetic ones. Next, the multi-valued logic network is optimized using our methods of symbolic functional decomposition, designed for functions with multi-valued inputs and multi-valued outputs. Finally, the whole circuit is implemented in FPGA device using commercially available tools. The goal of the presented methodology is to minimize the total FPGA area. Presented example showed that our methodology gives better results than existing RTL synthesis tools.