Title :
Graphical presentation of integrated circuit critical areas for lithographic defects
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Serbia
Abstract :
Extraction of the integrated circuit critical areas associated with short and open circuits is considered. A local layout extraction approach has been applied. The performance of the proposed approach is illustrated on two layout examples by visualization of the equivalent critical areas applying an extraction system PRELAY/EXACCA/GRAPH.
Keywords :
"Integrated circuit layout","Integrated circuit modeling","Data mining","Circuit faults","Visualization","Predictive models","Integrated circuit yield","Circuit simulation","Inspection","Optimization methods"
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.503353
