DocumentCode :
3632438
Title :
Combining internal scan chains and boundary scan register: A case study
Author :
Zoran Stamenkovic;Mary Giles;Francisco Russi
Author_Institution :
IHP GmbH, Frankfurt (Oder), Germany
fYear :
2009
Firstpage :
2064
Lastpage :
2069
Abstract :
The paper presents a Design-For-Testability (DFT) approach for System-on-Chips (SOC) that combines internal scan chains and boundary scan register (BSR) into a single scan register known as Scan-Through-TAP (STT) methodology. We are using the IEEE Standard 1149.1 Instruction as a user defined instruction (UDI) to control the internal scan chains operation via TDI and TDO saving the scan pins, and allowing accessibility of the internal scan chains at the board level through the TAP controller.
Keywords :
"System testing","Design for testability","Automatic test pattern generation","System-on-a-chip","Test pattern generators","Circuit faults","Circuit testing","Registers","Logic testing","Flip-flops"
Publisher :
ieee
Conference_Titel :
EUROCON 2009, EUROCON ´09. IEEE
Print_ISBN :
978-1-4244-3860-0
Type :
conf
DOI :
10.1109/EURCON.2009.5167932
Filename :
5167932
Link To Document :
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