FPGA implementation of an acoustic echo canceller using a VSS-NLMS algorithm

Many interesting adaptive algorithms have been proposed for acoustic echo cancellation. Even if they exhibit good performance in “infinite” precision, their capabilities could be seriously affected when using practical implementation platforms, e.g., digital signal processor (DSP) or field-programmable gate array (FPGA). In this context, several finite-precision effects could seriously bias the acoustic echo canceller (AEC) behavior. In this paper, we present an FPGA implementation of an AEC based on a recently proposed variable step-size normalized least-mean-square (VSS-NLMS) algorithm. Area and speed results are provided for a XC2S600E chip. The overall performance of this AEC indicates that it could be a reliable solution for real-world acoustic echo cancellation scenarios.