Title :
Some simulated properties of the pseudostructure of a floating gate MOS transistor
Author :
Daniela Durackova;Mario Krajmer;Juraj Racko;Juraj Breza;Magdalena Kadlecikova
Author_Institution :
Department of Microelectronics, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Ilkovi?ova 3, 812 19 Bratislava, Slovakia
fDate :
5/1/2009 12:00:00 AM
Abstract :
The floating gate technology is widely used as a memory element in digital circuits and as a novel memory element in analogue technology. In this work we prepare the basis for on-chip implementation of a Cellular Neural Network (CNN). For this purpose we investigate the features of a pseudo-floating gate transistor introduced in [1]. After simulating the structure by T-CAD tool we designed a behavioural model in SPICE that could be implemented into CADENCE design tool.
Keywords :
"MOSFETs","Nonvolatile memory","Doping","Cellular neural networks","Threshold voltage","Virtual colonoscopy","Microelectronics","Information technology","Digital circuits","Network-on-a-chip"
Conference_Titel :
Electronics Technology, 2009. ISSE 2009. 32nd International Spring Seminar on
Print_ISBN :
978-1-4244-4260-7
Electronic_ISBN :
2161-2064
DOI :
10.1109/ISSE.2009.5207000
