Title :
An approximation method for modeling a CMOS bit-level product cell
Author :
Yesenia E. Gonzalez-Navarro;Felipe Gomez-Castaneda;Jose A. Moreno-Cadenas
Author_Institution :
VLSI Lab., Solid-State Electronics Section, Department of Electrical Engineering, CINVESTAV-IPN, Mexico City, Mexico
Abstract :
An approximation method for a CMOS bit-level product cell used for vector-matrix multiplications is presented. The quantitative mathematical model of the cell is obtained by using CID/CCD principles to understand the device function and employing MOS structure equations to describe the cell operation. Due to the resultant equation cannot be solved explicitly, a multilayer artificial neural network is proposed to do functions approximations. The resultant algorithm is used to create an electrical device model for PSPICE simulations.
Keywords :
"Approximation methods","Semiconductor device modeling","Charge coupled devices","Electrodes","Equations","Artificial neural networks","Voltage control","Clocks","SPICE","Logic"
Conference_Titel :
Circuits and Systems, 2009. MWSCAS ´09. 52nd IEEE International Midwest Symposium on
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1558-3899
DOI :
10.1109/MWSCAS.2009.5235911
