A.2 CDM at the nanoscale frontier

Summary form only given, as follows. A record of the workshop was not made available for publication as part of the conference proceedings. This workshop will explore the CDM ESD effects from different perspectives that now challenge the robustness of semiconductor products. 1) Technology scaling: How do new processes, materials and device structures affect CDM sensitivity? Can new process, devices, or circuit techniques be developed to counteract these increasing sensitivities? 2) Application performance challenges: How will the challenges of complex chip integration and mixed signal circuit blocks be overcome? What are the protection / performance tradeoffs for RF and ultra-high speed serial communications links? 3) Chip-level & packaging design issues: What challenges are faced in integrating multiple voltage domains, mixed signal elements, RF circuits in a digital chip? How does packaging affect CDM performance, and can package design be optimized for improved CDM protection? 4) CDM qualifications: Will the industry need to lower its expectations of on-chip protection, and place more emphasis on reducing ESD exposure on the manufacturing floor? Are our CDM test methods even representative of real world CDM stresses? You are also invited to send your comments to the workshop moderator at info@esda.org, with the topic "2006 ESD Symposium Workshop" in the subject line.