DocumentCode :
3633229
Title :
Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA
Author :
Tomasz Kryjak;Marek Gorgon
Author_Institution :
Department of Automatics, AGH University of Science and Technology, Cracow, Poland
fYear :
2009
Firstpage :
373
Lastpage :
378
Abstract :
The article presents a pipeline implementation of the block cipher CLEFIA. The article examines three known methods of implementing a single encryption round and proposes a new fourth method. The article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. The article contains a detailed analysis of the data processing path for the 128-bit key version of the algorithm and verifies its operation on two FPGA cards in practice. On the basis of one of these cards, the article proposes a prototype of an effective supercomputer-compatible hardware accelerator (High Performance Computing Application).
Keywords :
"Pipelines","Field programmable gate arrays","Table lookup","Cryptography","Circuits","Delay","Data processing","Hardware","Logic","Throughput"
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on
ISSN :
1946-147X
Electronic_ISBN :
1946-1488
Type :
conf
DOI :
10.1109/FPL.2009.5272264
Filename :
5272264
Link To Document :
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