A radix-8 complex divider for FPGA implementation

We present a design of a radix-8 complex division for fixed-point operands suitable for FPGA implementation. The design, consisting of operands´ prescaling and digit recurrence, shares logic resources and optimizes the use of 6-input LUTs of FPGA devices for efficient design. An optimized single table for prescaling factors is developed. The design is implemented in Altera Stratix-II FPGA for several operands precisions and compared in cost, latency and power with a design using non-shared resources and with an IP-based design. The results show advantages of the proposed design in cost, delay, and power.