Random numbers generation: Investigation of narrowtransitions suppression on FPGA

Random number generators play an important role in the field of cryptography and security. It is often required that a random number generator consists of digital logic blocks only, so that it can be implemented on reconfigurable platforms. Since randomness cannot be proved by statistical tests there is a need for a provably secure hardware random number generator. In order to provide a proof of security, an experimental investigation of various physical effects on reconfigurable platforms is needed. In this paper we focus on the effect of narrow transitions suppression in the logic gates. The estimation of this effect may be crucial for the validity of the security proof of a RNG design. We explain our views on how experiments on FPGA should be performed and we give description of the measurement setup. We show that up to 98% of the transitions are suppressed in our experimental FPGA setup.